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The focus of these cards is typically for the E5/E7 servers.Īlso aimed at high density, but also for the lowest total cost of ownership, are the new E3-1500 v5 CPUs using second generation eDRAM and Iris Pro graphics with Skylake cores. These can be added into any system similar to GPUs or MICs, making it platform agnostic.
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While we are under the impression that Intel will start to integrate FPGA functionality in their main product lines over the next decade, but at this point an FPGA is the peak perf/watt solution.įor users who want compute density, in a limited space, Intel offers its Visual Compute Accelerator through partners, and these cards put three Iris Pro enabled processors from the last generation on a single 225W PCIe card.
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The performance-per-watt element of the stack is the Altera Arria family of FPGAs, now that Altera is formally merged with Intel. Intel likes to promote that their solution line covers both cloud and communications with a range of applicable products. After introducing processors with embedded DRAM (code named Crystal Well) combined with the Broadwell CPU architecture last generation in a variety of solutions, Intel are now expanding their lines depending on the quality, cost or speed required by the customer. Intel’s focus on video conversion and delivery systems is not small. Alternatively, Intel lists the performance for AVC-to-HEVC 1080p30 capture and encode for 15 simultaneous streams, suitable for a multi-camera live event. For HEVC, the top 45W part is reported as supporting, in real-time, two streams doing HEVC to HEVC 4K30 transcodes (essentially splitting a scene in two directions). While we’re unlikely to get these units in hand anytime soon, Intel’s listed the performance of the top 45W part as up to 26% faster in a synthetic benchmark over the previous generation Broadwell edition at 65W: most of this will be down to the increase in execution units between the two. This means that the 4+3e is most likely a cut-down version of a 4+4e chip, with part of the graphics disabled. At the launch of Intel’s Skylake platform, and more recently at events, Intel’s silicon roadmap only afforded two variants of Iris Pro: 2+4e with 64 MB of eDRAM, or 4+4e with 128 MB of eDRAM. The P555 arrangement uses only 48 EUs, or Intel’s GT3, with 128 MB of embedded DRAM, making it GT3e. The E3-1558L v5, using Iris Pro Graphics P555, is an extreme oddball of the bunch.
Xeon quicksync plus#
We were told by Intel that there are no plans to release socketable versions of these processors at this time, meaning that the mock up design of the processor on the Intel slide below is just for show, and not a real representation of these parts.Īll the processors have Iris Pro Graphics P580, which affords the largest implementation of Intel’s Gen 9 integrated graphics at 72 execution units (72 EUs), along with the largest application of embedded DRAM at 128 MB – this is colloquially known as GT4e, giving a 4+4e silicon die (four cores plus GT4e). All CPUs will be soldered down ‘BGA’ models to be directly embedded into the motherboard. The main performance differentiator between them all is the frequency of the processor, with the E3-1558L v5 will also have a slightly cut down version of Iris Pro graphics. These fit between Intel’s E3-1200 v5 Xeon processors, which are standard Skylake based Xeons up to four cores, and Intel’s E5-1600/2600 v4 Broadwell-based Xeons with up to 22 cores in a single socket: Intel Xeon Familiesįive processors are set to be released under the E3-1500 v5 name, one at 65W, three at 45W, and one at 35W. These are Skylake based CPUs, using four cores with hyperthreading, but are backed with Iris Pro graphics with the 72 execution units available and a redesigned embedded DRAM to accelerate computation over the previous generation.
Xeon quicksync series#
In line with this, Intel is releasing their new E3-1500 v5 series of processors with a primary focus on Intel Quick Sync. Traditionally there are three ways to do this: raw CPU horsepower, FPGAs, custom fixed-function ASICs, or GPUs. Moving from HD to FHD and 4K as well as 360-degree video requires a lot of immediate compute power in order to keep up with the event being filmed, as well as keeping enough quality in tow to maintain the user experience. The rise of video stream services, especially live services, has accelerated the need for dynamic and on-the-fly conversion of video content and the infrastructure to do so.